The present invention relates to a unified process for the fabrication of complementary metal oxide semiconductor (CMOS) and silicon nitride oxide semiconductor (SNOS) devices on a common wafer, with provisions for polycrystalline silicon (poly) resistors, and poly and diffused interconnects. In particular, the present process features the fabrication of SNOS type electrically erasable programmable read only memories (EEPROMs) and nonvolatile random access memories (NVRAMs) formed in electrically isolated wells to provide means for erasing and writing of data at the bit level.
Processes which are suitable to fabricate CMOS devices or nonvolatile SNOS type memory cells have been the subject of extensive individual development and refinement in recent years. As an example, consider the subject matter in U.S. Pat. No. 4,380,804 by inventors Lockwood et al., and in the U.S. patent applications having Ser. Nos. 352,734 and 332,037, now U.S. Pat. No. 4,422,885, by inventors Dham et al. and Brower et al., respectively, all commonly assigned to the assignee of the present application. From the teachings in the latter two, one is apprised of the fundamentals in the fabrication of CMOS devices by the formation of wells, and the formation of conventional field effect transistors (FETs) in combination SNOS type memory cells on a common chip but with the selectively retained regions of silicon nitride (nitride) layer. Heretofore, a unified process has generally been considered too complex, in view of the anticipated count of the masking operations and the complexity of the overall process mix. The dissuading effects become particularly pronounced when one recognizes that the memory dielectric in the SNOS type memory device is degraded as to its fundamental data retention characteristic if the wafer is subjected to any high temperature fabrication environments after the formation of the memory dielectric.